7.1.28 HPAC - AC Hi-Pot (EHT)
Hi-Pot or EHT testing (to check for insulation breakdown between windings or between windings and the screen or core) is often specified for power line transformers or for switched mode power transformers in applications where safety is important.
It is typically performed between all primary windings connected together, and all secondary windings plus the screen connected together.
SPECIFYING THE MEASUREMENT
During the test, an ac voltage is applied across two groups of windings with the windings in each group being shorted together. The voltage and current are monitored throughout the dwell time; if either the test voltage cannot be maintained, or the current is too large, then a failure will be recorded.
In programming the AT3600 you may select the voltage (from 100V to 5kVrms), the frequency (50Hz / 60Hz at the full voltage, or up to 1kHz at reduced voltage), the current trip level (10μA to 30mApeak), and the ramp up and dwell times, all to suit the specification of the transformer under test.
Many transformer specifications require Hi-Pot testing to be carried out with a dwell time of 60 seconds. Although the transformer must be designed and constructed to meet this, it is common practice to reduce the dwell time for production testing.
This is recognised by IEC 742, which permits a dwell time of 2 seconds for production testing. Although not required by IEC 742, it is good practice to increase the test voltage by say 10% when performing reduced-time testing, to provide additional security for the test.
IEC742 has been replaced by IEC61558, which specifies 1 second for production testing. Details are available on the IEC web-site (http://www.iec.ch).
During a Hi-Pot test, the Wattage is continuously monitored and adjusted to provide the correct output. If the programmed output voltage cannot be maintained, the tester will automatically display ‘FAIL’, illuminate the red indicator, return a ‘FAIL’ to the server (if used) and sound a warning buzzer (if enabled). This method complies with the production requirements of EN61558-1 (1998), UL1411, 5th Edition and others.
Under certain test conditions the measured current will be higher than the allowed minimum limit due to parasitic effects on the AT3600 and any connected fixture system. The maximum parasitic effect created by the AT3600 with every node being used on an HPAC test can be calculated by:
Ip = V*(4.614*10-10 + 9.1*10-11*f) where V = Test voltage and f = test frequency.
This works out to be 12.5uA at 2.5KV @ 50Hz.